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| IPD50N06S3-15 OptiMOS(R)-T Power-Transistor Product Summary V DS R DS(on),max ID 55 15 50 V m A Features * N-channel - Normal Level - Enhancement mode * Automotive AEC Q101 qualified * MSL1 up to 260C peak reflow * 175C operating temperature * Green package (RoHS compliant) * 100% Avalanche tested PG-TO252-3-11 Type IPD50N06S3-15 Package PG-TO252-3-11 Marking 3N0615 Maximum ratings, at T j=25 C, unless otherwise specified Parameter Continuous drain current1) Symbol ID Conditions T C=25 C, V GS=10 V T C=100 C, V GS=10 V2) Pulsed drain current2) Avalanche energy, single pulse2) Avalanche current, single pulse Gate source voltage3) Power dissipation Operating and storage temperature IEC climatic category; DIN IEC 68-1 I D,pulse E AS I AS V GS P tot T j, T stg T C=25 C T C=25 C I D=25 A Value 50 35 200 130 50 20 65 -55 ... +175 55/175/56 mJ A V W C Unit A Rev. 1.2 page 1 2009-05-20 IPD50N06S3-15 Parameter Symbol Conditions min. Values typ. max. Unit Thermal characteristics2) Thermal resistance, junction - case SMD version, device on PCB R thJC R thJA minimal footprint 6 cm2 cooling area4) Electrical characteristics, at T j=25 C, unless otherwise specified Static characteristics Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current V (BR)DSS V GS=0 V, I D= 1 mA V GS(th) I DSS V DS=V GS, I D=30 A V DS=55 V, V GS=0 V, T j=25 C V DS=55 V, V GS=0 V, T j=125 C2) Gate-source leakage current Drain-source on-state resistance I GSS RDS(on) V GS=20 V, V DS=0 V V GS=10 V, I D=25 A 55 2.1 3.0 0.01 4 1 A V 2.3 62 40 K/W - 1 1 13 100 100 15 nA m Rev. 1.2 page 2 2009-05-20 IPD50N06S3-15 Parameter Symbol Conditions min. Values typ. max. Unit Dynamic characteristics2) Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Gate Charge Characteristics2) Gate to source charge Gate to drain charge Gate charge total Gate plateau voltage Reverse Diode Diode continous forward current2) Diode pulse current2) Diode forward voltage Reverse recovery time2) Reverse recovery charge2) 1) C iss C oss Crss t d(on) tr t d(off) tf V DD=27.5 V, V GS=10 V, I D=50 A, R G=18 V GS=0 V, V DS=25 V, f =1 MHz - 2980 450 430 24 59 24 67 3400 675 645 - pF ns Q gs Q gd Qg V plateau V DD=11 V, I D=50 A, V GS=0 to 10 V - 24 10 43 7.5 32 15 50 - nC V IS I S,pulse V SD t rr Q rr T C=25 C V GS=0 V, I F=50 A, T j=25 C V R=27.5 V, I F=I S, di F/dt =100 A/s - 0.9 20 25 50 200 1.3 - A V ns nC Current is limited by bondwire; with an R thJC = 2.0 K/W the chip is able to carry 52 A at 25C. For detailed information see Application Note ANPS071E. 2) Defined by design. Not subject to production test. 3) Qualified at -5V and +20V 4) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 m thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.2 page 3 2009-05-20 IPD50N06S3-15 1 Power dissipation P tot = f(T C); V GS 6 V 2 Drain current I D = f(T C); V GS 6 V 70 60 60 50 50 40 P tot [W] 40 I D [A] 0 50 100 150 200 30 30 20 20 10 10 0 0 0 50 100 150 200 T C [C] T C [C] 3 Safe operating area I D = f(V DS); T C = 25 C; D = 0 parameter: t p 1000 4 Max. transient thermal impedance Z thJC = f(t p) parameter: D =t p/T 101 0.5 1 s 10 0 100 10 s 0.1 I D [A] 100 s Z thJC [K/W] 10-1 0.05 1 ms 10 10-2 0.01 single pulse 1 0.1 1 10 100 10-3 10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 V DS [V] t p [s] Rev. 1.2 page 4 2009-05-20 IPD50N06S3-15 5 Typ. output characteristics I D = f(V DS); T j = 25 C parameter: V GS 200 20 V 12 V 6 Typ. drain-source on-state resistance R DS(on) = f(I D); T j = 25 C parameter: V GS 100 5V 6V 7V 8V 9V 90 80 10 V 160 70 R DS(on) [m] 120 I D [A] 9V 60 50 40 30 20 10 80 8V 40 7V 6V 5V 10 V 0 0 2 4 6 8 10 0 20 40 60 80 100 120 V DS [V] I D [A] 7 Typ. transfer characteristics I D = f(V GS); V DS = 6 V parameter: T j 200 8 Typ. drain-source on-state resistance R DS(on) = f(T j); I D = 50 A; V GS = 10 V 24 150 -55 C 20 100 175 C R DS(on) [m] 25 C I D [A] 16 50 12 0 0 2 4 6 8 10 8 -60 -20 20 60 100 140 180 V GS [V] T j [C] Rev. 1.2 page 5 2009-05-20 IPD50N06S3-15 9 Typ. gate threshold voltage V GS(th) = f(T j); V GS = V DS parameter: I D 4 10 Typ. capacitances C = f(V DS); V GS = 0 V; f = 1 MHz 104 3.5 Ciss 300A 3 Coss V GS(th) [V] C [pF] 30A 2.5 Crss 103 2 1.5 1 -60 -20 20 60 100 140 180 102 0 5 10 15 20 25 T j [C] V DS [V] 11 Typical forward diode characteristicis IF = f(VSD) parameter: T j 103 12 Typ. avalanche characteristics I AV = f(t AV) parameter: T j(start) 100 10 2 150C 100C 25C I AV [A] 101 175 C 25 C I F [A] 10 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1 0.1 1 10 100 1000 V SD [V] t AV [s] Rev. 1.2 page 6 2009-05-20 IPD50N06S3-15 13 Typical avalanche Energy E AS = f(T j) parameter: I D 280 12.5 A 14 Drain-source breakdown voltage V BR(DSS) = f(T j); I D = 1 mA 65 240 60 200 E AS [mJ] 160 25 A V BR(DSS) [V] 55 120 80 50 A 50 40 0 0 50 100 150 200 45 -60 -20 20 60 100 140 180 T j [C] T j [C] 15 Typ. gate charge V GS = f(Q gate); I D = 50 A pulsed parameter: V DD 12 11 V 44 V 16 Gate charge waveforms V GS Qg 10 8 V plateau V GS [V] 6 V g s(th) 4 2 Q g (th) Q gs 0 10 20 30 40 50 60 70 80 Q sw Q gd Q gate 0 Q gate [nC] Rev. 1.2 page 7 2009-05-20 IPD50N06S3-15 Published by Infineon Technologies AG 81726 Munich, Germany (c) Infineon Technologies AG 2009 All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1.2 page 8 2009-05-20 IPD50N06S3-15 Revision History Version Date Changes Removal of feature: ultra low 04.10.2007 Rdson Implementation of avalanche 04.10.2007 current single pulse Data Sheet version 1.1 Data Sheet version 1.1 Data Sheet version 1.1 04.10.2007 Update of package drawing Update of avalanche diagram 12 07.11.2007 and 13 implementation of footnote 2 for 07.11.2007 Eas specification Correction of marking and update 20.05.2009 of disclaimer Data Sheet version 1.1 Data Sheet version 1.1 Data Sheet version 1.2 Rev. 1.2 page 9 2009-05-20 |
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